Okmetic Bonded Silicon On Insulator wafers offer advanced platform for MEMS sensors and power devices, which in many cases are more cost-effective choice than bulk silicon wafers. BSOI wafers have many benefits as they enable more ambitious device designs, improved device performance and smaller die size and they can be fully customized to meet your device and process needs.
Okmetic BSOI wafers are manufactured by bonding two silicon wafers together leaving an insulating buried oxide layer between them. Typically sensing elements and possible IC applications are built on the top wafer acting as a device layer. The buried oxide layer is an excellent electric insulating layer and it also forms an effective etch-stop in device manufacturing. It can also act as a sacrificial layer when manufacturing more complex devices such as released MEMS structures. The handle wafer is supporting the structure but can also be utilized in sealing the structure or as part of the sensing element. SOI wafers’ quality and cleanliness requirements are identical with bulk silicon wafers.
Bonding enables thicker SOI device layer than competing
technologies, which gives more device design freedom
Thanks to Okmetic’s bonding process, the device layer of the SOI wafer can be made much thicker than with competing SOI technologies, which gives more freedom to device design. The Bonded SOI wafer device layer can range from 1 μm to over 200 μm with standard thickness tolerance being ±0.5 µm and even ±0.1 µm with Enhanced SOI. Okmetic’s superior orientation accuracy capability can be utilized in both device layer and handle wafer, which enables smaller variation in customer’s device performance. Handle wafer thicknesses between 300 µm and 950 µm are possible and back surface can be polished or etched. Buried oxide is high quality thermally grown SiO2.
BSOI is optimal for variety of applications
Okmetic BSOI solutions are used e.g. for advanced pressure sensors, microfluidic components, MOEMS, flow sensors, actuators, 3-axis accelerometers, gyroscopes and silicon microphones. They also offer a new type of solution for the manufacturers of high voltage applications such as gate drivers (IGBT/Power MOSFET), smart power/high voltage BCD and lateral HV devices. In addition, SOI wafers usage is expanding into RF applications, for the needs of which Okmetic has developed High Resistivity SOI wafers. The possibility to tailor and modify parameters helps reach the full potential of any design idea in advanced device development.
TYPICAL SOI SPECIFICATIONS
|Growth method||Cz, MCz, A-MCz®|
|Crystal orientation||<100>, <110>,<111>|
|N type dopants||Phosphorus, red phosphorus|
|P type dopants||Boron|
|Resistivity||From < 0.001 to > 7,000 Ohm-cm|
|Device layer thickness||From 1 μm to > 200 μm
Tolerance ±0.5 μm (standard BSOI), ±0.3 μm (0.3 SOI),
±0.1 μm (E-SOI®), ±0.7 μm (C-SOI®)
|Buried oxide layer thickness||
From 0.3 μm to 4 μm, typically between 0.5 μm
|Handle wafer thickness||From 300 μm to 950 μm, typically 725 μm in 200mm wafer and 380 μm in 150mm
Back surface polished or etched
BSOI enables more ambitious device designs cost-effectively
SOI wafers offer extremely cost-effective solution over bulk silicon micromachining. As an example, when manufacturing a pressure sensor on 400 µm thick wafer the cost per chip can be reduced by 33% compared to bulk silicon micromachining. This is because BSOI allows smaller die sizes and more chips per wafer thus reducing the wafer, patterning, etching and bonding costs.
The BSOI wafer enables the design of more advanced applications thanks to its layered structure and possibility for a thicker device layer adding the design freedom. For example, expansion of smart power management integrations to include High Voltage driver circuits up to 100V or beyond are possible when using BSOI as a platform.
BSOI wafer is an advanced solution with multiple benefits:
- reduced device size and cost
- Improved device performance and precision
- increased reliability
- more advanced device designs
BSOI variations for specialized needs
Okmetic 0.3-SOI is a bonded Silicon On Insulator wafer, which has buried oxide (BOX) layer between a bottom handle wafer and a top silicon wafer that is thinned with extra precision to achieve improved ±0.3 μm device layer thickness tolerance. This improved device uniformity is a relatively cost-effective solution enabling improved device performance and precision and additional freedom to device design. Even higher uniformity can be achieved with Okmetic E-SOI®. The 0.3-SOI wafer is beneficial platform for many MEMS applications such as pressure sensors and resonators.