Power wafer line

Okmetic Power wafer line provides an optimal platform for the manufacture of various power devices. Our power device optimized wafer solutions improve power device performance, reduce Total Cost of Ownership and enable more refined designs.  

Okmetic has been supplying wafers for power devices for decades. Wafers targeted for discrete power devices have been in the portfolio since the 1990’s whilst Power GaN Substrate wafers and Power Management SOI wafers were first introduced in the 2010’s.  Power wafers’ capabilities are developed continuously in collaboration with customers. Okmetic power wafers enable the manufacture of power devices used in renewable energy solutions, electric cars, portable consumer products, as well as different solutions related to power management and efficiency improvement.  

Okmetic’s power device optimized wafers are mainly manufactured with our signature Advanced Magnetic Czochralski (A-MCz®) crystal growth method, which coupled with wide selection of wafer parameters guarantee customized, high value-added wafer solutions with reduced power losses.  

Line of power device optimized wafers 

Okmetic power wafer line consists of specialty wafers reaching down to <0.001 Ohm-cm of bulk resistivities. Different wafer types include 150 to 200 mm SSP, DSP and SOI wafers. Wafer resistivity, crystal orientation, oxygen content, and thickness can be customized to match your device or process needs. Okmetic provides wide range of wafer thicknesses from 380 to 1,150 μm. In mixed metal lattices like GaN epi layers, thicker wafers endure the extreme stresses of the epitaxial processes. Our sales and technical support are happy to help finding the optimal solution, customized for your needs. 

Okmetic Power wafer line comprise: 

A-MCz® crystal growth method vs FZ method 

  1. Better availability than FZ in 200 mm
  2. Availability in <111> orientation
  3. Optimized Oi range to increase wafer strength at customer process. Less prone to slip and breakage.

General SSP and DSP wafer specifications for Power semiconductors

Growth methodCz, MCz, A-MCz®
Diameter150 mm, 200 mm
Crystal orientation<100>, <110>, <111>
N type dopantsArsenic, Phosphorus
P type dopantsBoron
ResistivityDown to < 0.001 Ohm-cm
SSP thickness200 mm: 550 to 1,150 µm*
150 mm: 400 to 1,150 µm
*Other thicknesses possible with certain limitations
DSP thickness200 mm: 380 to 1,150 µm*
150 mm: 380 to >1,150 µm
*Other thicknesses possible with certain limitations
SSP backside treatmentEtched, Polyback, LTO
Fully CMOS compatible wafer surface quality and cleanliness requirements  

General SOI wafer specifications for Power semiconductors

Growth method Cz, MCz, A-MCz®
Diameter 150 mm, 200 mm
Crystal orientation <100>, <110>, <111>
N type dopants Phosphorus
P type dopants Boron
Resistivity Down to <0.001 Ohm-cm
Device layer thicknessFrom 1 μm to >200 μm
Tolerance down to ±0.1 μm (200 mm), ±0.2 μm (150 mm)
Buried oxide layer thicknessFrom 0.3 μm to 4 μm, typically between 0.5 μm and 2 μm
Type: thermal oxide
Handle wafer thickness200 mm: 300 μm to 950 μm, typically 725 μm
150 mm: 300 μm to 950 μm, typically 675 μm
Tolerance ± 5 µm (± 3 µm for demanding devices)
Back surfacePolished or Etched
Terrace areaStandard or Terrace Free (Available for 200 mm)
Fully CMOS compatible wafer surface quality and cleanliness requirements  

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