Power Management SOI wafers
Okmetic Power Management SOI wafers are Bonded Silicon On Insulator wafers combining down to <0.001 Ohm-cm resistivity and tight resistivity control with low and controlled Oi levels and zero BMDs. They provide a perfect platform for power device gate drivers, Battery and Power Management ICs, Intelligent Power Modules, and other Smart Power devices using advanced BCD or BiCMOS processes.
Okmetic has been supplying SOI wafers for power management devices in high volumes ever since 2015. Power Management SOI wafers are cutting edge power substrates enabling reduced power losses. The wafers are manufactured by bonding two silicon wafers together and leaving an insulating buried oxide layer between them. The bonding technology enables thicker device layer for high power density needs of miniaturized chips. Fully customizable buried oxide layer thickness guarantees improved isolation for power management devices.
Power Management SOI wafers enable higher current densities and improved isolation
Our signature Advanced Magnetic Czochralski, A-MCz®, crystal growth method is one of the factors adding value to Power Management SOI wafers. The process enables SOI wafers with down to <0.001 Ohm-cm resistivity, tight resistivity control, low and controlled Oi levels and zero BMDs. All these factors are highly beneficial for power management devices.
In addition to Power Management SOI wafers, Okmetic also supplies SOI wafers for GaN-on-Si applications. Read more about using SOI wafers as Power GaN Substrate wafers.
Fully customizable SOI wafer solutions meeting Power Management device requirements
Power Management SOI wafers are a good match for various devices e.g. power device gate drivers (IGBT, Power MOSFET, SiC MOSFET, GaN HEMT), Battery and Power Management ICs, Intelligent Power Modules, and other Smart Power applications using advanced BCD or BiCMOS processes.
Power Management SOI wafers are a good match e.g. for power device gate drivers, Battery and Power Management ICs, Intelligent Power Modules and other Smart Power applications using advanced BCD or BiCMOS processes
Okmetic Power Management SOI properties are fully customizable. The device layer thickness of Power Management SOI is freely adjustable between 1.0 µm and >200 µm and the thickness tolerance is as low as ±0.1 µm (200 mm wafer) or ±0.2 µm (150 mm wafer). The thicker device layer’s benefit is that it enables higher operating current densities. The buried oxide layer thickness is also freely adjustable between 0.5 µm and 4 µm. Power Management SOI wafers are also available as Terrace Free SOI wafers providing maximized usable area.
As with other Okmetic Silicon On Insulator wafers, the Power Management SOI wafer can be customized to match your exact device and process needs. Our sales and technical support are happy to help in customization and selection of wafer parameters to find an optimal solution for your needs.
Power Management SOI wafers vs. bulk silicon wafers
SOI wafers offer extremely cost-effective solution over bulk silicon wafers. This is because SOI wafers’ layered structure allow reduced die sizes and more chips per wafer in addition to providing more design freedom. SOI wafers that are optimized for power management device needs also enable higher voltages and improved isolation as well as design for high common-mode transient immunity (CMTI).
One of the Power Management SOI wafers’ key benefits compared to bulk silicon wafers is that the buried oxide layer and trench isolation enable monolithic integration of low, medium and high voltage blocks on the same chip while reducing the chip size. Power Management SOI wafers also reduce device layer induced leakage currents and generate no substrate-induced leakage currents. In addition, latch-up prevention and improved ESD/EMI protection compared to bulk silicon wafers are among the key benefits.
Power Management SOI wafer has multiple benefits:
- Effortless and more compact integration of devices operating at different voltages (low and high voltages) on a same chip
- Reduced device size and improved reliability
- Reduced leakage currents minimizing power losses
- No parasitic latch-up phenomena among isolated transistors
- High temperature resilience facilitating design of high performance ICs operating in harsh environments
- Enables design for high common-mode transient immunity (CMTI)
Power Management SOI wafer specifications
|Growth method||Cz, MCz, A-MCz®|
|Diameter||150 mm, 200 mm|
|Crystal orientation||<100>, <111>|
|N type dopants||Antimony, Phosphorus|
|P type dopants||Boron|
|Resistivity||Down to <0.001 Ohm-cm*|
*Resistivity range varies by dopant and orientation
|Device layer thickness||From 1 μm to >200 μm |
Tolerance down to ±0.1 μm (200 mm), ±0.2 μm (150 mm)
|Buried oxide layer thickness||From 0.3 μm to 4 μm, typically between 0.5 μm and 2 μm |
Type: thermal oxide
|Handle wafer thickness||200 mm: 300 μm to 950 μm, typically 725 μm|
150 mm: 300 μm to 950 μm, typically 675 μm
Tolerance ±5 µm (±3 µm for demanding devices)
|Back surface||Polished or Etched|
|Terrace area||Standard or Terrace Free (Available for 200 mm)|