Wafers for Power

Okmetic SSP, DSP and SOI wafers optimized for the needs of high-performing power semiconductors include highly doped, low resistivity wafers and medium resistivity wafers with tight resistivity control, low and controlled Oi level as well as zero BMDs. A-MCz® crystal growth method coupled with wide selection of wafer parameters guarantee customized, high value-added wafer solutions with reduced power losses.

Okmetic’s decades-long crystal growth expertise provides the foundation also for our wafer portfolio for power semiconductors. Our highly doped, low-resistivity wafers and medium resistivity wafers with tight resistivity control, low and controlled Oi level as well as zero BMDs enable extremely high performing power semiconductors with reduced power losses.

Power MOSFETs, IGBTs, diodes, CMOS, BiCMOS and bipolar transistors all benefit from wafers that are specifically tailored for their needs.

Okmetic’s low resistivity wafers are widely used e.g. in power MOSFETs and low voltage power MOSFETs in particular as well as in Schottky and power diodes, bipolar transistors, rectifiers and thyristors. Our medium resistivity wafers optimized for power devices are used in IGBTs as well as CMOS and BiCMOS processes.

Lowest resistivities down to < 0.001 Ohm-cm

Okmetic has wide selection of 150 to 200mm low and medium resistivity wafers tailored for the needs of power semiconductors. Wafer parameters can be freely adjusted according to customer needs and the lowest resistivities achievable are down to < 0.001 Ohm-cm. The selection of dopants include phosphorus, arsenic and boron. Crystal orientations include <100>, <110> or <111>. Wafer thicknesses range from 380 to >1,150 µm and backside treatment can be etched, polyback, LTO or polished.

Our low resistivity wafers and especially the ones doped with phosphorus enable customers to make misfit-free epilayers with very low metal impurity levels leading to better device performance.

A-MCz® crystal growth method beneficial for IGBTs

The medium resistivity wafers manufactured with our advanced MCz (A-MCz®) crystal growth method have shown excellent performance and cost-effectiveness over wafers manufactured with FZ method. Our A-MCz® wafers have also increased the yields of customers’ processes as their enhanced lattice robustness reduces dislocations and breakage and their level of bulk micro defects is extremely low. Donor generation effects and precipitation behavior can also be taken into account by adjusting Oi level accordingly.

Benefits of Ultra low Oi A-MCz® crystal growth method:

  • Better slip resistance and radiation hardness compared to FZ.
  • Very low Oi level is possible.
  • No Bulk Micro Defects.
  • Excellent for High Voltage applications (like IGBT).

Advanced power platforms: SOI wafers and wafers for GaN-on-Si

Okmetic has been supplying Bonded SOI wafers for power management devices since 2015. They have shown to add value for Power devices requiring trench dielectric isolation. These devices include gate drivers such as Power MOSFETs as well as embedded technologies such as smart power / BCD and lateral HV devices.

Okmetic has been in the forefront developing silicon wafers to match the demanding GaN epi process needs the power device manufacturers encounter. Various wafer design characteristics determine how the silicon wafers behave in GaN epi process and Okmetic’s experience enables to design silicon wafers that best withstand the demanding GaN epi process conditions. GaN-on-Si platforms’ popularity is rising as they offer a cost-effective platform for higher voltage power devices challenging existing GaN-on-SiC platforms. Silicon wafers’ benefit over silicon carbide wafers is that they are readily available in 200 mm diameter. Okmetic has also developed high resistivity RF GaN wafers for GaN-on-Si applications.

Further development can be made by utilizing SOI wafers as the GaN-on-Si substrate for instance in building new HEMT devices (High-Electron-Mobility Transistor). GaN layers grown on SOI wafers exhibits lower stress and higher crystalline quality according to x-ray diffraction than the layers grown on standard silicon substrates. The buried oxide beneath the SOI wafers’ device layer reduces parasitic induction and when combined with trench isolation, enables monolithic integration of the power and logic part leading to smaller die footprint.

SSP and DSP wafer specifications for Power semiconductors

Growth methodCz, MCz, A-MCz®
Diameter150 mm, 200 mm
Crystal orientation<100>, <110>, <111>
N type dopantsArsenic, Phosphorus
P type dopantsBoron
ResistivityDown to < 0.001 Ohm-cm
SSP thickness150 mm: 400 to 1,150 µm; 200 mm: 550 to 1,150 µm
DSP thickness150 mm: 380 to 1,150 µm; 200 mm: 380 to 1,150 µm*
*Other thicknesses possible with certain limitations
SSP backside treatmentEtched, Polyback, LTO

SOI wafer specifications for Power semiconductors

Growth method Cz, MCz, A-MCz®
Diameter 150 mm, 200 mm
Crystal orientation <100>, <110>, <111>
N type dopants Phosphorus
P type dopants Boron
Resistivity Down to < 0.001 Ohm-cm
Device layer thicknessFrom 1 μm to > 200 μm
Tolerance ± 0.5 μm (standard BSOI), ± 0.3 μm (0.3 SOI), ± 0.1 μm (E-SOI®)
Buried oxide layer thicknessFrom 0.3 μm to 4 μm, typically between 0.5 μm and 2 μm
Type: thermal oxide
Handle wafer thicknessFrom 300 μm to 950 μm, typically 725 μm in 200 mm wafer and 675 μm in 150 mm wafers
Tolerance ± 5 µm (± 3 µm for demanding devices)
Back surfacePolished or Etched
TTV<1 µm
Orientation accuracy±.2° (±.1° for demanding devices)

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